Understanding CIC Decimation Filters for Feedback Control

What is a CIC Filter?

A Cascaded Integrator-Comb (CIC) filter is a class of FIR filter that performs decimation (sample rate reduction) without requiring any multipliers. This makes them exceptionally efficient on FPGAs, where multiplier resources (DSP slices) are limited and valuable.

The key insight: a CIC filter is equivalent to a cascade of moving-average filters, implemented as the combination of integrator stages (running at the high rate) and comb stages (running at the low rate).

Our Implementation

In our feedback controller, the CIC filter serves a critical role: reducing the 125 MSPS ADC sample rate to 1 MSPS for the PID controller. This gives the PID controller more time to compute while also reducing high-frequency noise.

Parameters

Bit Growth

The maximum bit growth of a CIC filter is:

B_max = N × ceil(log₂(R)) = 6 × 7 = 42 bits

So the output can be up to 14 + 42 = 56 bits wide. We use 64-bit internal accumulators for convenience, then normalize back to 14 bits using a fixed-point scaler.

The Scaler

The CIC filter has a DC gain of R^N = 125^6 ≈ 3.814 × 10¹². To normalize this back to unity gain, we multiply by the inverse:

assign dout_raw = (din * 302231) >>> 60;

The constant 302231 = round(2^60 / 125^6) provides the correct normalization with minimal error.

Trade-offs

CIC filters have a sinc^N frequency response, which means:

• •Excellent stopband rejection near multiples of the output sample rate
• •Passband droop that increases with frequency (correctable with a compensation filter)
• •No multipliers required — pure additions and subtractions

For our feedback control application, the passband droop is acceptable because the PID controller's bandwidth is typically much less than the 1 MSPS output rate. The key advantage is the dramatic reduction in noise bandwidth, which improves the signal-to-noise ratio for the PID controller.