April 7, 2026·Quanta Control

Digital Lock-In Amplification on FPGA: From PDH Locking to Modulation Transfer Spectroscopy

lock-in amplifierPDHFPGASystemVerilogcavity lockingoptical

The Lock-In Principle: Extracting Signals from Noise

In precision optics, we often need to measure a signals that is buried deep within the noise floor. Whether it's the reflection from a high-finesse Fabry-Pérot cavity or a weak spectroscopy signal, simple DC detection is often insufficient due to $1/f$ noise and detector drift.

The Lock-In Amplifier solves this by shifting the measurement to a known modulation frequency $f_{mod}$ . By multiplying the input signal by a reference sine wave and low-pass filtering the result, we can extract the component of the signal that is phase-coherent with our reference, effectively creating a bandpass filter with an extremely high Q-factor.

DDS Reference Generation

The heart of a digital lock-in is the Direct Digital Synthesis (DDS) engine. On an FPGA, we implement this using a phase accumulator and a Look-Up Table (LUT).

For正交解调 (Quadrature Demodulation), we need both a sine ( $I$ ) and a cosine ( $Q$ ) reference:

I(t) = \sin(2\pi f_{mod} t + \phi)

Q(t) = \cos(2\pi f_{mod} t + \phi)

In SystemVerilog, a 32-bit phase accumulator provides sub-Hz frequency resolution at a 125 MHz clock:

// 32-bit Phase Accumulator
always_ff @(posedge clk) begin
    phase_acc <= phase_acc + phase_inc;
end
 
// Sin/Cos LUT Lookup
assign sin_ref = lut_sin[phase_acc[31:22]]; // 10-bit LUT address
assign cos_ref = lut_cos[phase_acc[31:22]];

Quadrature Demodulation

Once we have our references, we multiply them by the incoming digitized signal $S(t)$ . According to the product-to-sum identities:

S(t) \cdot \sin(\omega t) = \frac{1}{2}A[\cos(\omega t - \omega t - \theta) - \cos(2\omega t + \theta)]

After low-pass filtering, the high-frequency $2\omega$ term is removed, leaving only the DC component which is proportional to the signal amplitude and phase:

X = \frac{1}{2}A \cos(\theta), \quad Y = \frac{1}{2}A \sin(\theta)

In our FPGA implementation, these multiplications happen in parallel using dedicated DSP48 slices, ensuring zero-latency demodulation.

Low-Pass Filtering: The CIC Advantage

To extract the DC error signal, we need a steep low-pass filter. As discussed in our CIC filter deep-dive, a Cascaded Integrator-Comb filter is ideal here. It provides excellent stopband rejection at multiples of the decimation rate, which we typically set to match our modulation frequency to suppress residuals.

Application: PDH Cavity Locking

The most powerful application of this architecture is Pound-Drever-Hall (PDH) locking. In a PDH setup:

•We modulate the laser phase at a high frequency (typically 10–50 MHz).
•The reflection from the cavity carries the phase-encoded error signal.
•We demodulate the reflected signal on the FPGA to generate the Error Signal.

The PDH error signal has a characteristic "dispersion-like" shape near resonance. Because the FPGA handles the demodulation digitally, we avoid the offsets and phase drifts inherent in analog mixers.

// PDH Demodulator logic
assign mixed_signal = adc_data * local_oscillator;
// Followed by CIC Decimation to extract the slow error signal

Phase Recovery and CORDIC

While PDH often only requires the $X$ (in-phase) component, some applications (like vector network analysis) require the absolute amplitude and phase. For this, we implement the CORDIC (Coordinate Rotation Digital Computer) algorithm to compute:

R = \sqrt{X^2 + Y^2}

\theta = \operatorname{atan2}(Y, X)

The CORDIC engine provides these values using only shifts and additions, making it extremely efficient for real-time FPGA processing.

Full Loop Integration

By integrating the Lock-In amplifier with our PID controller, we create a complete, autonomous locking system. The laser phase is modulated by the DDS, the reflected signal is demodulated in the PL, and the resulting error signal is fed into the PID to drive the laser's frequency actuator—all with a total loop latency of less than 200ns.

Summary

Digital lock-in amplification on FPGA brings a level of stability and precision to optical experiments that was previously only available with expensive, standalone laboratory instruments. By implementing the entire chain—from DDS to PID—on a single SoC, we eliminate the noise and drift associated with analog signal paths.

In our next post, we will look at how we use Allan Deviation to verify the performance of these locks and identify the fundamental noise floors of our system.